The present specification relates to a method of making a semiconductor switch device and to a semiconductor switch device.
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) can be used as electric switches for high Radio Frequency (RF) signals. For these applications the device does not actually switch at high frequencies, rather it passes or blocks RF signals. Best performance is achieved with a device that combines low series resistance in on-state with low input capacitance in off-state. One of the most popular ways to evaluate the overall performance of an RF Switch MOSFET is to calculate a figure of merit (FOM), which is defined as the product of the on-state resistance (Ron) and the off-state capacitance (Coff).
During transistor operations, electrons travel in the channel of an NMOSFET. At the drain side of the channel, where the electrical field is usually maximum, a few electrons can gain a sufficiently high kinetic energy to overcome the Si—SiO2 energy barrier and be injected into the gate oxide. Those electrons are called “hot” since their energy is (much) higher than that of electrons in thermal equilibrium with the silicon lattice. Hot electrons can also produce impact ionization in the silicon and create new electron-hole pairs which, in turn, may be injected into the gate oxide. Part of injected electrons may be trapped in electron traps, in the SiO2 or at its interface with Si (dangling bonds), where they may induce a change (degradation) of the electrical characteristics of the device. Energetic electrons injected into the SiO2 may also create new traps. In order to reduce hot-carrier injection effects, the electric field at the drain side of the channel may be reduced by smoothening the doping profile. This may be achieved by implanting a shallow region of Arsenic or Phosphorus (in case of NMOS), with a reduced concentration with respect to the drain implant. This lightly doped drain (LDD) region may also play a role in reducing the series resistance of the channel.
However, use of an LDD in a MOSFET may generally result in an increase in the overlap capacitance of the device, that is, the gate-to-source (Cgs) and gate-to-drain (Cgd) capacitances. The overlap capacitance may constitute significant fraction of the total off-state capacitance (Coff) of the device, as shown in the following formulas:
            C      off        =                            (                                    1                                                C                  dd                                -                                  C                  ds                                                      +                          1                                                C                  ss                                -                                  C                  ds                                                              )                          -          1                    +              C        ds                        C      ss        =                  C        sd            +              C        sg            +              C        sb                        C      dd        =                  C        ds            +              C                  d          ⁢                                          ⁢          g                    +              C        db                        C      gg        =                  C        gs            +              C        gd            +                        C          gb                .            
Where Cds is the channel capacitance, and Csb, Cdb and Cgb are the source to bulk, drain to bulk and gate to bulk capacitances, respectively.